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fedl610q482-02 issue date: may.9, 2014 ML610Q482/ml610482 8-bit microcontroller 1/32 general description this lsi is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i 2 c bus interface (master), buzzer driver, battery level detect circuit, and rc oscillation type a/d converter, are incorporated around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. the flash rom that is installed as progra m memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask rom and is most suitable for battery-driven applications. the on-chip debug function that is installed enables program debugging and programming. the ML610Q482p/ ml610482p supporting industrial temperature -40 c to +85 c, are also available. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function (ML610Q482) ? minimum instruction execution time 30.5 s (@32.768 khz system clock) 0.244 s (@4.096 mhz system clock) ? internal memory ? ML610Q482 internal 64kbyte flash rom (32k 16 bits) (including unusable 1kbyte test area) internal 4kbyte data ram (4096 8 bits) ? ml610482 internal 64kbyte mask rom (32k 16 bits) (including unusable 1kbyte test area) internal 4kbyte data ram (4096 8 bits) ? interrupt controller ? 2 non-maskable interrupt sources (inte rnal source: 1, external source: 1) ? 18 maskable interrupt sources (internal sources: 14, external sources: 4) ? time base counter ? low-speed time base counter 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter 1 channel ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s @32.768 khz) ? timers ? 8 bits 4 channels (timer0-3: 16-bit x 2 configuration available by using timer0-1 or timer2-3) ? clock frequency measurement mode (in one channel of 16-bit configuration using timer2-3)
fedl610q482-02 ML610Q482/ml610482 2/32 ? pwm ? resolution 16 bits 1 channel ? synchronous serial port ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? txd/rxd 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400 kbps@4mh ), standard mode (100 kbps@1mh , 50kbps@500khz) ? buzzer driver ? 4 output modes, 8 frequencies, 16 duty levels ? rc oscillation type a/d converter ? 24-bit counter ? time division 2 channels ? analog comparator ? operating voltage: v dd =1.8v 3.6v ? common mode input voltage: 0.2v vdd 1.0v ? input offset voltage: 50mv(max) ? interrupt allow edge selection and sampling selection ? general-purpose ports ? non-maskable interrupt input port 1 channel ? input-only port 6 channels (including secondary functions) ? output-only port 4 channels (including secondary functions) ? input/output port 22 channels (including secondary functions) ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset when oscillation stop of the low-speed clock is detected ? reset by the watchdog timer (wdt) overflow ? power supply voltage detect function ? judgment voltages: one of 16 levels ? judgment accuracy: 2% (typ.) ? clock ? low-speed clock: (this lsi can not guarantee the operation withou low-speed clock) crystal oscillation (32.768 khz/38.4khz) ? high-speed clock: built-in rc oscillation (500 khz) built-in pll oscillation (8.192 mhz 2.5%), crystal/ceramic oscillation (4.096 mhz), external clock ? selection of high-speed clock mode by software: built-in rc oscillation, built-in pll oscillation, crystal/ceramic oscillation, external clock
fedl610q482-02 ML610Q482/ml610482 3/32 ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals. ? guaranteed operating range ? operating temperature: ? 20 c to +70 c (p version: ?40 c to +85 c) ? operating voltage: v dd = 1.1v to 3.6v ? product name ? s upported function - chip (die) - rom type operating temperature product availability ML610Q482- wa flash rom -20c to +70c yes ML610Q482p- wa flash rom -40c to +85c yes ml610482- wa mask rom -20c to +70c yes ml610482p- wa mask rom -40c to +85c yes -48-pin plastic tqfp - rom type operating temperature product availability ML610Q482- tb flash rom -20c to +70c yes ML610Q482p- tb flash rom -40c to +85c yes ml610482- tb mask rom -20c to +70c - ml610482p- tb mask rom -40c to +85c - xxx: rom code number q:flash rom version p: wide range temperature version wa: chip tb: tqfp
fedl610q482-02 ML610Q482/ml610482 4/32 block diagram ML610Q482 block diagram figure 1 show the block diagram of the ML610Q482. "*" indicates the secondary function of each port. figure 1 ML610Q482 block diagram program memory (flash) 64kbyte ssio sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 1 ram 4096byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 int 1 pwm gpio p00 to p03 p10 , p11 p20, p21, p22, p24 int 9 nmi p30 to p35 p40 to p47 pa0 to pa7 data-bus pwm0* test reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power v ddl rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v pp v dd v ss v ddx int 1 analog comparator cmpp cmpm int 1 buzzer bz0*
fedl610q482-02 ML610Q482/ml610482 5/32 ml610482 block diagram figure 2 show the block diagram of the ml610482. "*" indicates the secondary function of each port. * secondary function or tertiary function figure 2 ml610482 block diagram program memory (mask rom) 64kbyte ssio sck0* sin0* uart i 2 c sda* scl* int 1 ram 4096byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 int 1 pwm gpio p00 to p03 p10 , p11 p20, p21, p22, p24 int 5 nmi p30 to p35 p40 to p47 pa0 to pa7 data-bus pwm0* test reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power v ddl rc-adc 2 cs0* in0* rs0* rt0* rct0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss v ddx int 1 analog comparator cmpp cmpm int 1 buzzer bz0* rxd0* txd0*
fedl610q482-02 ML610Q482/ml610482 6/32 pin configuration ML610Q482 tqfp48 pin layout (flash rom version only) note: the assignment of the pads p30 to p35 are not in order. figure 3 ML610Q482 tqfp48 pin configuration p22 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 p21 p20 vss pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 cmpp cmpm p00 p01 p02 p03 vss p24 p40 p41 p42 p43 vdd p11/osc1 p10/osc0 vss vpp nmi reset_n test p47 p46 p45 p44 p30 p31 p34 p32 p33 p35 vdd vddl vss vddx xt0 xt1
fedl610q482-02 ML610Q482/ml610482 7/32 ML610Q482 chip pin layout & dimension p22 p21 p20 vss pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 nc 36 35 34 33 32 31 30 29 28 27 26 25 nc nc) nc) nc) nc) nc) nc) p30 37 24 vdd p31 38 23 p11/osc1 p34 39 22 p10/osc0 p32 40 21 vss p33 41 20 vpp p35 42 19 nmi vdd 43 18 reset_n vddl 44 17 test vss 45 16 p47 vddx 46 15 p46 xt0 47 14 p45 xt1 48 13 p44 nc) nc) nc) nc) nc) nc) nc) 1 2 3 4 5 6 7 8 9 10 11 12 nc cmpp cmpm p00 p01 p02 p03 vss p24 p40 p41 p42 p43 (nc): no connection note: the assignment of the pads p30 to p35 are not in order. chip size: 2.76 mm 3.00 mm pad count: 48 pins minimum pad pitch: 100 m pad aperture: 80 m 80 m chip thickness: 350 m voltage of the rear side of chip: v ss level figure 4 ML610Q482 chip layout & dimension 3.00mm 2.76mm
fedl610q482-02 ML610Q482/ml610482 8/32 ML610Q482 pad coordinates table 1 ML610Q482 pad coordinates chip center: x=0,y=0 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 cmpp -1036.0 -1380.0 25 pa0 1023.0 1380.0 2 cmpm -830.0 -1380.0 26 pa1 775.0 1380.0 3 p00 -730.0 -1380.0 27 pa2 651.0 1380.0 4 p01 -482.0 -1380.0 28 pa3 403.0 1380.0 5 p02 -382.0 -1380.0 29 pa4 279.0 1380.0 6 p03 -134.0 -1380.0 30 pa5 31.0 1380.0 7 vss -34.0 -1380.0 31 pa6 -93.0 1380.0 8 p24 219.0 -1380.0 32 pa7 -341.0 1380.0 9 p40 327.0 -1380.0 33 vss -458.0 1380.0 10 p41 655.0 -1380.0 34 p20 -666.0 1380.0 11 p42 775.0 -1380.0 35 p21 -766.0 1380.0 12 p43 1023.0 -1380.0 36 p22 -1032.0 1380.0 13 p44 1260.0 -912.0 37 p30 -1260.0 922.0 14 p45 1260.0 -778.0 38 p31 -1260.0 769.0 15 p46 1260.0 -530.0 39 p34 -1260.0 521.0 16 p47 1260.0 -426.0 40 p32 -1260.0 417.0 17 test 1260.0 -167.0 41 p33 -1260.0 169.0 18 reset_n 1260.0 -67.0 42 p35 -1260.0 67.0 19 nmi 1260.0 181.0 43 vdd -1260.0 -122.0 20 vpp 1260.0 281.0 44 vddl -1260.0 -333.0 21 vss 1260.0 411.0 45 vss -1260.0 -503.0 22 p10 1261.3 610.0 46 vddx -1260.0 -673.0 23 p11 1261.3 858.0 47 xt0 -1260.0 -773.0 24 vdd 1260.0 1010.0 48 xt1 -1260.0 -1021.0
fedl610q482-02 ML610Q482/ml610482 9/32 ml610482 chip pin layout & dimension note: the assignment of the pads p30 to p35 are not in order. chip size: 2.44 mm 2.46mm pad count: 48 pins minimum pad pitch: 100 m pad aperture: 80 m 80 m chip thickness: 350 m voltage of the rear side of chip: v ss level figure 5 ml610482 chip layout & dimension 36 16 15 xt1 xt0 vddx vss vddl vdd 48 p35 p33 47 46 45 p32 p34 44 43 p31 p30 42 vdd p11/osc1 p10/osc0 vss nmi reset_n test p47 p46 p45 p44 p22 p21 p20 vss pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 17 18 21 19 22 24 23 30 31 32 33 34 35 28 29 1 2 3 cmpp cmpm p00 p03 14 13 27 25 26 40 39 38 37 y x 2.46 mm 2.44 mm 41 6 p02 5 vss 7 p24 8 p40 9 p41 10 p42 11 p43 4 p01 12
fedl610q482-02 ML610Q482/ml610482 10/32 ml610482 pad coordinates table 2 ml610482 pad coordinates chip center: x=0,y=0 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 cmpp -1010 -1110 25 pa0 1025 1110 2 cmpm -804 -1110 26 pa1 777 1110 3 p00 -704 -1110 27 pa2 653 1110 4 p01 -456 -1110 28 pa3 405 1110 5 p02 -356 -1110 29 pa4 281 1110 6 p03 -108 -1110 30 pa5 33 1110 7 vss -8 -1110 31 pa6 -91 1110 8 p24 205 -1110 32 pa7 -339 1110 9 p40 313 -1110 33 vss -451 1110 10 p41 641 -1110 34 p20 -659 1110 11 p42 761 -1110 35 p21 -759 1110 12 p43 1009 -1110 36 p22 -1025 1110 13 p44 1100 -842 37 p30 -1100 844 14 p45 1100 -708 38 p31 -1100 691 15 p46 1100 -460 39 p34 -1100 443 16 p47 1100 -356 40 p32 -1100 339 17 test 1100 -97 41 p33 -1100 91 18 reset_n 1100 3 42 p35 -1100 -11 19 nmi 1100 251 43 vdd -1100 -212 20 44 vddl -1100 -312 21 vss 1100 351 45 vss -1100 -434 22 p10 1100 524 46 vddx -1100 -574 23 p11 1100 772 47 xt0 -1100 -694 24 vdd 1100 885 48 xt1 -1100 -942 note: padno.20 does not exist.
fedl610q482-02 ML610Q482/ml610482 11/32 pin list primary function secondary function tertiary function pad no. pin name i/o function pin name i/o function pin name i/o function 7,21, 33,45 vss ? negative power suppl y pin ? ? ? ? ? ? 24,43 v dd ? positive power supply pin ? ? ? ? ? ? 44 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? ? ? 46 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? ? ? ? 20 v pp ? power supply pin for flash rom ? ? ? ? ? ? 17 test i/o input/output pin for testing ? ? ? ? ? ? 18 reset_ n i reset input pin ? ? ? ? ? ? 47 xt0 i low-speed clock oscillation pin ? ? ? ? ? ? 48 xt1 o low-speed clock oscillation pin ? ? ? ? ? ? 19 nmi i non-maskable interrupt pin ? ? ? ? ? ? 3 p00/exi 0 i input port, external interrupt 0, capture 0 input ? ? ? ? ? ? 4 p01/exi 1 i input port, external interrupt 1, capture 1 input ? ? ? ? ? ? 5 p02/exi 2/rxd0 i input port, external interrupt 2, uart0 receive ? ? ? ? ? ? 6 p03/exi 3 i input port, external interrupt 3 ? ? ? ? ? ? 1 cmpp i analog comparator non-inverted input ? ? ? ? ? ? 2 cmpm i analog comparator inverted input ? ? ? ? ? ? 22 p10 i input port osc0 i high-speed oscillation ? ? ? 23 p11 i input port osc1 o high-speed oscillation ? ? ? 34 p20/le d0 o output port lsclk o low-speed clock output ? ? ? 35 p21led 1 o output port outclk o high-speed clock output ? ? ? 36 p22/le d2 o output port bz0 o bz0 output ? ? ? 8 p24/le d4 o output port pwm0 o pwm0 output ? ? ? 37 p30 i/o input/output port in0 i rc type adc0 oscillation input pin ? ? ? 38 p31 i/o input/output port cs0 o rc type adc0 reference capacitor connection pin ? ? ? 40 p32 i/o input/output port rs0 o rc type adc0 reference resistor connection pin ? ? ? 41 p33 i/o input/output port rt0 o rc type adc0 resistor sensor connection pin ? ? ? 39 p34 i/o input/output port rct0 o rc type adc0 resistor/capacitor sensor connection pin pwm0 o pwm0 output
fedl610q482-02 ML610Q482/ml610482 12/32 primary function secondary function tertiary function pad no. pin name i/o function pin name i/o function pin name i/o function 42 p35 i/o input/output port rcm o rc type adc oscillation monitor ? ? ? 9 p40 i/o input/output port sda i/o i 2 c data input/output sin0 i ssio data input 10 p41 i/o input/output port scl i/o i 2 c clock input/output sck0 i/o ssio synchronous clock 11 p42 i/o input/output port rxd0 i uart data input sout0 i ssio data output 12 p43 i/o input/output port txd0 o uart data output pwm0 o pwm output 13 p44/t02 p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input in1 i rc type adc1 oscillation input pin sin0 i ssio0 data input 14 p45/t13 p1ck i/o input/output port, timer 1/timer 3 external clock input cs1 o rc type adc1 reference capacitor connection pin sck0 i/o ssio0 synchronous clock 15 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin sout0 o ssio0 data output 16 p47 i/o input/output port rt1 o rc type adc1 resistor sensor connection pin ? ? ? 25 pa0 i/o input/output port ? ? ? ? ? ? 26 pa1 i/o input/output port ? ? ? ? ? ? 27 pa2 i/o input/output port ? ? ? ? ? ? 28 pa3 i/o input/output port ? ? ? ? ? ? 29 pa4 i/o input/output port ? ? ? ? ? ? 30 pa5 i/o input/output port ? ? ? ? ? ? 31 pa6 i/o input/output port ? ? ? ? ? ? 32 pa7 i/o input/output port ? ? ? ? ? ? note: * 1 a vpp terminal exists only ML610Q482.
fedl610q482-02 ML610Q482/ml610482 13/32 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and v ss as required. ? ? osc0 i secondary ? osc1 o crystal/ceramic connection pin for high-speed clock. a crystal or ceramic is connected to this pin (4.1 mhz max.). capacitors cdh and cgh (see measuring circuit 1) are connected across this pin and v ss . this pin is used as the secondary function of the p10 pin(osc0) and p11 pin(osc1). secondary ? lsclk o low-speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00-p03 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p10,p11 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose output port p20,p21, p22,p24 o general-purpose output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose input/output port p30-p35 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p40-p47 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive pa0-pa7 i/o general-purpose input/output port. primary positive
fedl610q482-02 ML610Q482/ml610482 14/32 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/se condary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the tertiary function of the p24 or p43 or p34 pin. tertiary positive t02p0ck o pwm0 external clock input pin. this pin is used as the primary function of the p44 pin. primary ? external interrupt nmi i external non-maskable interrupt input pin. an interrupt is generated on both edges. primary positive/ negative exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00-p03 pins. primary positive/ negative timer t02p0ck i external clock input pin used for both timer 0 and timer 2. the clocks for these timers are selected by software. this pin is used as the primary function of the p44 pin. primary ? t13p1ck i external clock input pin used for both timer 1 and timer 3. the clocks for these timers are selected by software. this pin is used as the primary function of the p45 pin. primary ? buzzer bz0 o buzzer signal output pin. this pin is used as the secondary function of the p22 pin. secondary positive/ negative led drive led0,1,2,4 o nmos open drain output pins to drive led. these pins are used as the primary function of the p20,p21,p22,p24 pins. primary positive/ negative
fedl610q482-02 ML610Q482/ml610482 15/32 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? crt0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? analog comparator cmpp i non-inverted input pin. ? ? cmpm i inverted input pin. ? ? for testing test i/o input/output pin for testing. a pull-down resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors cl0 and cl1 (see measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? plus-side power supply pin (internally generated) for low-speed oscillation. capacitor cx (see measuring circuit 1) is connected between this pin and v ss . ? ? v pp ? power supply pin for programming flash rom. a pull-up resistor is internally connected. ? ? note: * 1 a vpp terminal exists only ML610Q482.
fedl610q482-02 ML610Q482/ml610482 16/32 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin termination v pp *1 open reset_n open test open nmi open p00 to p03 v dd or v ss p10, p11 v dd p20, p21, p22, p24 open p30 to p35 open p40 to p47 open pa0 to pa7 open cmpp,cmpm v dd * 1 a vpp terminal exists only ML610Q482. note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q482-02 ML610Q482/ml610482 17/32 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +4.6 v power supply voltage 2 v pp *1 ta = 25 c ? 0.3 to +9.5 v power supply voltage 3 v ddl ta = 25 c ? 0.3 to +3.6 v power supply voltage 4 v ddx ta = 25 c ? 0.3 to +3.6 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port3?a, ta = 25 c ? 12 to +11 ma output current 2 i out2 port2, ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 1.16 w storage temperature t stg ? ? 55 to +150 c *1 : ML610Q482 only recommended operating conditions (v ss = 0v) parameter symbol condition range unit ML610Q482, ml610482 ? 20 to +70 operating temperature t op ML610Q482p, ml610482p ? 40 to +85 c operating voltage v dd ? 1.1 to 3.6 v v dd = 1.1 to 3.6v 30k to 36k v dd = 1.3 to 3.6v 30k to 650k operating frequency (cpu) f op v dd = 1.8 to 3.6v 30k to 4.2m hz c l0 ? 1.0 30% capacitor externally connected to v ddl pin c l1 ? 0.1 30% f capacitor externally connected to v ddx pin c x ? 0.1 30% f
fedl610q482-02 ML610Q482/ml610482 18/32 clock generation circuit operating conditions (v ss = 0v) rating parameter symbol condition min. typ. max. unit low-speed crystal oscillation frequency f xtl ? ? 32.768k/38.4k ? hz recommended equivalent series resistance value of low-speed crystal oscillation r l ? ? ? 40k ? c l =6pf of crystal oscillation *2 ? 0 ? c l =9pf of crystal oscillation ? 6 ? low-speed crystal oscillation external capacitor *1 c dl /c gl c l =12pf of crystal oscillation ? 12 ? pf high-speed crystal/ceramic oscillation frequency f xth ? ? 4.0m / 4.096m ? hz c dh ? ? 24 ? high-speed crystal oscillation external capacitor c gh ? ? 24 ? pf *1 : the external c dl and c gl need to be adjusted in consideration of variation of internal loading capacitance c d and c g , and other additional capacitance such as pcb layout. *2 : when using a crystal oscillator c l = 6pf, there is a possibility that can not be adjusted by external c dl and c gl . operating conditions of flash rom (ML610Q482 only) (v ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase *1 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase *1 7.7 to 8.3 v write cycles c ep ? 10 cycles data retention y dr ? 10 years *1 : those voltages must be supplied to v ddl pin and v pp pin when programming and eraseing flash rom. v pp pin has an internal pulldown resister. conditions of analog comparator (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit common mode input voltage cmv in v dd = 1.8 to 3.6v 0.2 ? v dd 1 v input offset voltage v cmpof v dd = 1.8 to 3.6v, ta = 25 c ? ? 50 mv response time t cmp ? ? 100 wake-up time t cmpw v dd = 1.8 to 3.6v, ta = 25 c over drive = 100mv ? ? 3 circuit current (during operation) i cmp v dd = 1.8 to 3.6v,ta = 25 c ? 2 4 a 1
fedl610q482-02 ML610Q482/ml610482 19/32 dc characteristics (1/6) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c typ. ? 10% 500 typ. + 10% khz 500khz rc oscillation frequency f rc v dd = 1.3 to 3.6v ta = ? 40 to +85 c typ. ? 35% 500 typ. + 35% khz pll oscillation frequency* 4 f pll lsclk = 32.768khz v dd = 1.8 to 3.6v -2.5% 8.192 +2.5% mhz low-speed crystal oscillation start time* 2 t xtl ? ? 0.3 2 s 500khz rc oscillation start time t rc ? ? 50 500 s high-speed crystal oscillation start time* 3 t xth v dd = 1.8 to 3.6v D 2 20 pll oscillation start time t pll v dd = 1.8 to 3.6v D 1 10 low-speed oscillation stop detect time *1 t stop ? 0.2 3 20 ms reset pulse width p rst ? 200 ? ? reset noise elimination pulse width p nrst ? ? ? 0.3 s power-on reset activation power rise time t por ? ? ? 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 3 : use 4.096mhz crystal oscillator chc49sfwb (kyocera). * 4 : 1024 clock average. reset_n reset pulse width (p rst ) p rst vil1 vil1 vdd 0.9xv dd 0.1xv dd t por powe r -on reset activation power rise time (t por )
fedl610q482-02 ML610Q482/ml610482 20/32 dc characteristics (2/6) (vdd = 1.1 to 3.6v, vss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ld2?0 = 0h 1.35 ld2?0 = 1h 1.4 ld2?0 = 2h 1.45 ld2?0 = 3h 1.5 ld2?0 = 4h 1.6 ld2?0 = 5h 1.7 ld2?0 = 6h 1.8 ld2?0 = 7h 1.9 ld2?0 = 8h 2.0 ld2?0 = 9h 2.1 ld2?0 = 0ah 2.2 ld2?0 = 0bh 2.3 ld2?0 = 0ch 2.4 ld2?0 = 0dh 2.5 ld2?0 = 0eh 2.7 bld threshold voltage v bld v dd = 1.35 to 3.6v ld2?0 = 0fh typ. ? 2% 2.9 typ. +2% v bld threshold voltage temperature deviation ? v bld v dd = 1.35 to 3.6v ? 0.1 ? %/ c 1 dc characteristics (ML610Q482) (3/6) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c ? 0.2 0.5 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. ? ? ? 5 a ta = 25 c ? 0.5 1.3 supply current 2 idd2 cpu: in halt state (ltbc, wdt: operating* 2 * 4 ). high-speed oscillation: stopped. ? ? ? 6 a ta = 25 c ? 5 7 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 2 high-speed oscillation: stopped. ? ? ? 12 a ta = 25 c ? 70 85 supply current 4 idd4 cpu: in 500khz cr operating state. ? ? ? 100 a ta = 25 c ? 0.83 1 supply current 5 idd5 cpu: in 4.096mhz operating state* 2 .pll: in oscillating state. v dd = 1.8 to 3.6v ? ? ? 1.2 ma ta = 25 c ? 1.3 1.4 supply current 6 idd6 cpu: in 4.096mhz operating state.crystal/ceramic: in oscillating state. * 2 * 3 v dd = 3.0v ? ? ? 2.0 ma 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 3 : use 4.096mhz crystal oscillator hc49sfwb (kyocera). * 4 : significant bits of blkcon0~blkcon4 registers are all ?1?.
fedl610q482-02 ML610Q482/ml610482 21/32 dc characteristics (ml610482) (4/6) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c ? 0.2 0.5 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. ? ? ? 2.5 a ta = 25 c ? 0.5 1.3 supply current 2 idd2 cpu: in halt state (ltbc, wdt: operating* 2 * 4 ). high-speed oscillation: stopped. ? ? ? 3.5 a ta = 25 c ? 3 5 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 2 high-speed oscillation: stopped. ? ? ? 8 a ta = 25 c ? 40 65 supply current 4 idd4 cpu: in 500khz cr operating state. ? ? ? 75 a ta = 25 c ? 0.5 0.65 supply current 5 idd5 cpu: in 4.096mhz operating state* 2 .pll: in oscillating state. v dd = 1.8 to 3.6v ? ? ? 0.75 ma ta = 25 c ? 0.9 1.1 supply current 6 idd6 cpu: in 4.096mhz operating state.crystal/ceramic: in oscillating state. * 2 * 3 v dd = 3.0v ? ? ? 1.3 ma 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 3 : use 4.096mhz crystal oscillator hc49sfwb (kyocera). * 4 : significant bits of blkcon0~blkcon4 registers are all ?1?.
fedl610q482-02 ML610Q482/ml610482 22/32 dc characteristics (5/6) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ? ? voh1 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 iol1 = +0.5ma, v dd = 1.8 to 3.6v ? ? 0.5 iol1 = +0.1ma, v dd = 1.3 to 3.6v ? ? 0.5 output voltage 1 (p20, p21, p22, p24/2 nd function is selected) (p30?p35) (p40?p47) (pa0?pa7) vol1 iol1 = +0.03ma, v dd = 1.1 to 3.6v ? ? 0.3 output voltage 2 (p20, p21, p22, p24/2 nd function is not selected) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ? ? 0.5 output voltage 3 (p40, p41) vol3 iol3 = +3ma, v dd = 2.0 to 3.6v (when i 2 c mode is selected) ? ? 0.4 v 2 iooh voh = v dd (in high-impedance state) ? ? 1 output leakage (p20, p21, p22, p24) (p30?p35) (p40?p47) (pa0?pa7) *1 iool vol = v ss (in high-impedance state) ? 1 ? ? a 3 iih1 vih1 = v dd 0 ? 1 v dd = 1.8 to 3.6v ? 600 ? 300 ? 20 v dd = 1.3 to 3.6v ? 600 ? 300 -10 input current 1 (reset_n) iil1 vil1 = v ss v dd = 1.1 to 3.6v ? 600 ? 300 300 600 v dd = 1.3 to 3.6v 10 300 600 iih1 vih1 = v dd v dd = 1.1 to 3.6v 2 300 600 input current 1 (test) iil1 vil1 = v ss -1 ? ? v dd = 1.8 to 3.6v 2 30 200 v dd = 1.3 to 3.6v 0.2 30 200 iih2 vih2 = v dd (when pulled-down) v dd = 1.1 to 3.6v 0.01 30 200 v dd = 1.8 to 3.6v ? 200 ? 30 ? 2 v dd = 1.3 to 3.6v ? 200 ? 30 -0.2 iil2 vil2 = v ss (when pulled-up) v dd = 1.1 to 3.6v ? 200 ? 30 -0.01 iih2z vih2 = v dd (in high-impedance state) ? ? 1 input current 2 (nmi) (p00?p03) (p10, p11) (p30?p35) (p40?p47) (pa0?pa7) iil2z vil2 = v ss (in high-impedance state) ? 1 ? ? a 4
fedl610q482-02 ML610Q482/ml610482 23/32 dc characteristics (6/6) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit v dd = 1.3 to 3.6v 0.7 v dd ? v dd vih1 v dd = 1.1 to 3.6v 0.7 v dd ? v dd v dd = 1.3 to 3.6v 0 ? 0.3 v dd input voltage 1 (reset_n) (test) (nmi) (p00?p03) (p10, p11) (p31?p35) (p40?p43) (p45?p47) (pa0?pa7) *1 vil1 v dd = 1.1 to 3.6v 0 ? 0.2 v dd vih2 ? 0.7 v dd ? v dd input voltage 2 (p30, p44) vil2 ? 0 ? 0.3 v dd v 5 input pin capacitance (nmi) (p00?p03) (p10, p11) (p30?p35) (p40?p47) (pa0?pa7) cin f = 10khz v rms = 50mv ta = 25 c ? ? 5 pf ?
fedl610q482-02 ML610Q482/ml610482 24/32 measuring circuits measuring circuit 1 measuring circuit 2 xt0 xt1 p10/osc0 p11/osc1 32.768khz crystal 4.096mhz crystal c gh c dh a v dd v ss c v : 1 f c l1 : 0.1 f c x : 0.1 f c gh : 24pf c dh : 24pf 32.768khz crystal: c-001r (epson toyocom) 4.096mhz crystal: hc49sfwb (kyocera) c v input pins v v dd v ddl v ddx v ss vih vil output pins (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. (*2) (*1) v ddl c l1 c l0 v ddx c x
fedl610q482-02 ML610Q482/ml610482 25/32 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pins a v dd v ddl v ddx v ss output pins *3: measured at the specified output pins. (*3) input pins v dd v ddl v ddx v ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring input pins a v dd v ddl v ddx v ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) rs1
fedl610q482-02 ML610Q482/ml610482 26/32 ac characteristics (external interrupt) (v dd = 1.1 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ? 106.8 s ac characteristics (uart) (v dd = 1.3 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ? ? brt* 1 ? s receive baud rate t rbrt ? brt* 1 ? 3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency selected) set with the uart0 baud rate register (ua0brtl,h) and the uart0 mode register 0 (ua0mod0). t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) nmi, p00?p03 (both-edge interrupt) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610q482-02 ML610Q482/ml610482 27/32 ac characteristics (synchronous serial port) (v dd = 1.3 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) 10 ? ? s sclk input cycle (slave mode) t scyc when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 1 ? ? s sclk output cycle (master mode) t scyc ? ? sclk* 1 ? s when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) 4 ? ? s sclk input pulse width (slave mode) t sw when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 0.4 ? ? s sclk output pulse width (master mode) t sw ? sclk* 1 0.4 sclk* 1 0.5 sclk* 1 0.6 s when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) ? ? 500 sout output delay time (slave mode) t sd when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 240 ns when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) ? ? 500 sout output delay time (master mode) t sd when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 240 ns sin input setup time (slave mode) t ss ? 80 ? ? ns when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) 500 ? ? sin input setup time (master mode) t ss when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 240 ? ? ns when rc oscillation is active * 2 (v dd = 1.3 to 3.6v) 300 ? ? sin input hold time t sh when high-speed oscillation is active * 3 (v dd = 1.8 to 3.6v) 80 ? ? ns * 1 : clock period selected with s0ck3?0 of the serial port 0 mode register (sio0mod1) * 2 : when rc oscillation is selected with oscm1?0 of the frequency control register (fcon0) * 3 : when crystal/ceramic oscillation , built-in pll oscillation , or external clock input is selected with oscm1?0 of the frequency control register (fcon0) t sd sclk0* sin0* sout0* *: indicates the secondar y function of the p ort. t sd t ss t sh t sw t sw t scyc
fedl610q482-02 ML610Q482/ml610482 28/32 ac characteristics (i 2 c bus interface: standard mode 100kbit/s) (v dd = 1.8 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ac characteristics (i 2 c bus interface: fast mode 400kbit/s) (v dd = 1.8 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q482-02 ML610Q482/ml610482 29/32 ac characteristics (rc oscillation a/d converter) (v dd = 1.3 to 3.6v, v ss = 0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resistors for oscillation rs0, rs1, rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 ? ? k ? f osc1 resistor for oscillation = 1k ? 209.4 330.6 435.1 khz f osc2 resistor for oscillation = 10k ? 41.29 55.27 64.16 khz oscillation frequency vdd = 1.5v f osc3 resistor for oscillation = 100k ? 4.71 5.97 7.06 khz kf1 rt0, rt0-1, rt1 = 1khz 5.567 5.982 6.225 ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? rs to rt oscillation frequency ratio *1 vdd = 1.5v kf3 rt0, rt0-1, rt1 = 100khz 0.104 0.108 0.118 ? f osc1 resistor for oscillation = 1k ? 407.3 486.7 594.6 khz ? 49.76 59.28 72.76 khz ? 5.04 5.993 7.04 khz ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? rs to rt oscillation frequency ratio *1 vdd = 3.0v kf3 rt0, rt0-1, rt1 = 100khz 0.100 0.108 0.115 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor re sistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0 ? cs0 oscillation) f oscx (rt0-1 ? cs0 oscillation) f oscx (rt1 ? cs1 oscillation) kfx = f oscx (rs0 ? cs0 oscillation) , f oscx (rs0 ? cs0 oscillation) , f oscx (rs1 ? cs1 oscillation) (x = 1, 2, 3) note: - please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. - please make wiring to components (capacitor, resisteor and et c.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. *1: input logic circuit to determine the specified measuring conditions. v dd v ddl v ddx c l1 c l0 c x v ss c v rcm frequency measurement (f oscx ) input pins vih vil (*1) cs0 rt0 in1 cs1 rs1 rt1 ri0 cs0 rs0 rs0 rct0 ri0-1 ct0 rt0 ri1 cs1 rs1 rt1 in0 cvr0 cvr1 rt0, rt0-1, rt1: 1k ? ? ? ? cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf
fedl610q482-02 ML610Q482/ml610482 30/32 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl610q482-02 ML610Q482/ml610482 31/32 revision history page document no. date previous edition current edition description fedl610q482p-01 dec.9, 2009 ? ? formally edition 1 all all change header and footer 1,3,4,5,6, 7,9,12,14 ,1516,17, 18,21,22, 23,24 1,3,4,5,6, 7,,8,9,10, 11,13,16, 1718,19, 20,21,22, 23,26,27, 28,29 add ML610Q482, ml610482 and ml610482p 3 4 change from "shipment" to " product name ? supported function " - 18 18 19 change "reset" to "reset pulse width (p rst )" and " power-on reset activation power rise time (t por )". fedl610q482-02 may.9,2014 29 30 update package dimensions
fedl610q482-02 ML610Q482/ml610482 32/32 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2009-2014 lapis semiconductor co., ltd.

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